1. Field of the Present Invention
The present invention generally relates to data processing systems, and more specifically, to methods and apparatuses in the systems that reduce system latency.
2. History of Related Art
The evolution of the computer industry has been driven by the insatiable appetite of the consumer for ever increased speed and functionality. One species that the evolution has created is the multi-processor computer.
Multi-processor systems, in similarity to other computer systems, have many different areas that are ripe for improvement. One such area ripe for improvement results from the current design implementations for multi-processor systems. Specifically, these multi-processor systems have a number of bottlenecks that degrade their overall performance. For instance, those; and skilled in the art are well aware of the difficulty of increasing processor performance due to the inability to keep the processors and their respective caches supplied with instructions and/or data.
A major performance factor is the speed of the bus which attaches the main memory to the processors. A secondary affect is the I/O bandwidth that the system supports.
Reference now being made to FIG. 1 (Prior Art), a schematic diagram of a typical multi-processor computer system 100 is shown. The computer system 100 includes two processors 102 and 104, memory 105, memory controller 106, and Bus Unit Controllers (BUC) 108 and 110. Communication between the processors 102 and 104, and memory controller 106 is facilitated by the system bus 112. The memory controller 106 is coupled to the memory 105, and communicates with BUCs 108 and 110, and processors 102 and 104 via Mezzanine bus (e.g. PCI bus) 116 and System Bus 112, respectively. Each of the BUCs 108 and 100 include caches 108a and 110a, respectively, and are used for communicating with I/O subsystems.
The design of system 100 reduces the loading effect on the system bus 112 by only placing the processors 102, 104, and memory controller 106 thereon; while the BUCs 108 and 110 are located on the Mezzanine bus 116. This type of configuration also allows for a higher frequency design and a wider data configuration (i.e. increases the bandwidth from processors 102 and 104 to memory 105) than would be practical with a design where all devices were on the system bus 112.
The separate Mezzanine bus 116 used for communication between the memory controller 106 and the I/O subsystem(s) provides several advantages. For example, the flexibility of the system 100 for multiple and different types of I/O buses is increased. In yet a further example, if the I/O bus was to be issued directly from the memory controller 106, then the limit on the system 100 would be based on the number of I/O buses which could be integrated into the memory controller 106 (i.e. both a pin count and a silicon space issue for the design of the memory controller).
The configuration of system 100 also results in the total bandwidth of the I/O subsystem only being dependent on the data width and the frequency of the I/O Mezzanine bus 116, and therefore, not limited by the bandwidth of any individual I/O bus.
Unfortunately, the design of system 100 results in a problem where the number of cycles required to snoop cached data in the BUCs (108 and 110) from an address placed on the system bus 112 to snoop response back to the system bus 112 is relatively long; especially when compared to the number of cycles required by one of the processors 102 or 104 to snoop its associated caches. In fact, this time may even be longer than it takes to read the requested data from the memory 105 itself. Further, if all addresses were required to be snooped down to the Mezzanine bus 116, then the system 100 configuration would not achieve any increased performance over a system using a combined system and Mezzanine bus.
It would therefore be a distinct advantage to have a method and apparatus that would allow the data processing snoop latency to be substantially equal to that of the processor snoop latency. The present invention provides such a method and apparatus.